View DS1865T_3447734.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the ds1865 controls and monitors all the burst-mode transmitter and video receiver biasing functions for a passive optical network (pon) triplexer. it has an apc loop with tracking-error compensation that provides the reference for the laser driver bias current and a temper- ature-indexed lookup table (lut) that controls the mod- ulation current. it continually monitors for high output current, high bias current, and low and high transmit power with its internal fast comparators to ensure that laser shutdown for eye safety requirements are met with- out adding external components. six adc channels monitor v cc , internal temperature, and four external monitor inputs (mon1?on4) that can be used to meet transmitter and video receive signal monitoring require- ments. two digital-to-analog converter (dac) outputs are available for biasing the video receiver channel, and five digital i/o pins are present to allow additional moni- toring and configuration. applications optical triplexers with gepon, bpon, or gpon transceiver features ? meets gepon, bpon, and gpon timing requirements for burst-mode transmitters ? bias current control provided by apc loop with tracking-error compensation ? modulation current is controlled by a temperature-indexed lookup table ? laser power leveling from -6db to +0db ? two 8-bit analog outputs, one is controlled by mon4 voltage for video amplifier gain control ? internal direct-to-digital temperature sensor ? six analog monitor channels: temperature, v cc , mon1, mon2, mon3, and mon4 ? five digital i/o pins for additional control and monitoring functions ? comprehensive fault management system with maskable laser shutdown capability ? two-level password access to protect calibration data ? 120 bytes of password 1 protected nonvolatile memory ? 128 bytes of password 2 protected nonvolatile memory in main device address ? 128 bytes of nonvolatile memory located at a0h slave address ? i 2 c-compatible interface for calibration and monitoring ? operating voltage: 2.85v to 3.9v ? operating temperature range: -40c to +95c ? packaging: 28-pin lead-free tqfn (5mm x 5mm x 0.8mm) ds1865 pon triplexer control and monitoring circuit ______________________________________________ maxim integrated products 1 19-5044; rev 1; 11/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t&r = tape and reel. ordering information part temp range pin-package DS1865T+ -40c to +95c 28 tqfn-ep* DS1865T+t&r -40c to +95c 28 tqfn-ep* tqfn (5mm x 5mm x 0.8mm) top view 26 27 25 24 10 9 11 tx-d fetg v cc gnd n.c. *ep *exposed pad. 12 ben bias gnd m4dac mod dac1 mon4 1 2 4 5 6 7 20 21 19 17 16 15 n.c. n.c. scl sda tx-f v cc 3 18 28 8 23 13 losi d0 bmd d2 d3 d1 22 14 mon3 mon1 mon2 n.c. ds1865 pin configuration
ds1865 pon triplexer control and monitoring circuit 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +95?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on mon1?on4, ben, bmd, and tx-d pins relative to ground.................-0.5v to (v cc + 0.5v) (subject to not exceeding +6v) voltage range on v cc , sda, scl, d0?3, and tx-f pins relative to ground ...............................-0.5v to +6v operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature...................see j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) +2.85 +3.9 v high-level input voltage (sda, scl, ben) v ih:1 0.7 x v cc v cc + 0.3 v low-level input voltage (sda, scl, ben) v il:1 -0.3 0.3 x v cc v high-level input voltage (tx-d, losi, d0, d1, d2, d3) v ih:2 2.0 v cc + 0.3 v low-level input voltage (tx-d, losi, d0, d1, d2, d3) v il:2 -0.3 0.8 v dc electrical characteristics ( v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc (notes 1, 2) 5 10 ma output leakage (sda, tx-f, d0, d1, d2, d3) i lo 1a i ol = 4ma 0.4 low-level output voltage (sda, tx-f, fetg, d0, d1, d2, d3) v ol i ol = 6ma 0.6 v high-level output voltage (fetg) v oh i oh = 4ma v cc - 0.4 v fetg before recall (note 3) 10 100 na input-leakage current (scl, ben, tx-d, losi) i li 1a digital power-on reset pod 1.0 2.2 v analog power-on reset poa 2.1 2.75 v
ds1865 pon triplexer control and monitoring circuit _____________________________________________________________________ 3 analog input characteristics (bmd, txp-hi, txp-lo, hbias) ( v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units bm d , tx p - h i, tx p - lo ful l - s cal e v ol tag ev apc (note 4) 2.5 v hbias full-scale voltage 1.25 ma bm d input resistance 35 50 65 k resolution (note 4) 8 bits error t a = +25? (note 5) ? %fs integral nonlinearity -1 +1 lsb differential nonlinearity -1 +1 lsb temperature drift -2.5 +2.5 %fs analog output characteristics ( v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units bias current i bias (note 1) 1.2 ma i bias shutdown current i bias:off 10 100 na voltage at i bias 0.7 1.2 1.4 v mod full-scale voltage v mod (note 6) 1.25 v mod output impedance (note 7) 3 k v mod error t a = +25? (note 8) -2.5 +2.5 %fs v mod integral nonlinearity -3 +3 lsb v mod differential nonlinearity -1 +1 lsb v mod temperature drift -2 +2 %fs electrical characteristics (dac1 and m4dac) ( v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units dac output range 0 2.5 v dac output resolution 8 bits dac output integral nonlinearity -2 +2 lsb dac output differential nonlinearity -1 +1 lsb dac error t a = +25? -1.25 +1.25 lsb dac temperature drift -2 +2 % fs dac offset v cc = 2.85v to 3.6v -20 +20 ? maximum load -500 +500 ? maximum load capacitance 250 pf
timing characteristics (control loop and quick-trip) ( v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units first md sample following ben t first (note 9) remaining updates during ben t update (note 9) ben high time t ben:high 400 ns ben low time t ben:low 96 ns output-enable time following poa t init 10 ms bias and mod turn-off delay t off 5s bias and mod turn-on delay t on 5s fetg turn-on delay t fetg:on 5s fetg turn-off delay t fetg:off 5s binary search time t search (note 10) 5 13 bias s amp l es adc round-robin time t rr 75 ms ds1865 pon triplexer control and monitoring circuit 4 _____________________________________________________________________ parameter symbol conditions min typ max units thermometer error t err -40? to +95? 3.0 ? digital thermometer (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units input resolution vmon 610 ? supply resolution v cc 1.6 mv input/supply accuracy ( m on 1, m on 2, m on 3, m on 4, v c c ) a cc at factory setting 0.25 0.5 % fs (full scale) update rate for mon1, mon2, mon3, mon4 temp, or v cc t frame 30 45 ms input/supply offset ( m on 1, m on 2, m on 3, m on 4, v c c ) v os (note 14) 0 5 lsb m on1, mon 2, m on3, mon 4 2.5 factory setting v c c 6.5536 v analog voltage monitoring (v cc = +2.85v to +3.9v, t a = -40? to +95?, unless otherwise noted.)
ds1865 i 2 c ac electrical characteristics ( v cc = +2.85v to +3.9v, t a = -40? to +95?, timing referenced to v il(max) and v ih(min) .) (see figure 9.) parameter symbol conditions min typ max units scl clock frequency f scl (note 11) 0 400 khz clock pulse-width low t low 1.3 ? clock pulse-width high t high 0.6 ? bus-free time between stop and start condition t buf 1.3 ? start hold time t hd:sta 0.6 ? start setup time t su:sta 0.6 ? data in hold time t hd:dat 0 0.9 ? data in setup time t su:dat 100 ns rise time of both sda and scl signals t r (note 12) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 12) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? capacitive load for each bus line c b (note 12) 400 pf eeprom write time t w (note 13) 20 ms pon triplexer control and monitoring circuit _____________________________________________________________________ 5 nonvolatile memory characteristics (v cc = +2.85v to +3.9v) parameter symbol conditions min typ max units eeprom write cycles at +70? 50,000 note 1: all voltages are referenced to ground. current into ic is positive, out of the ic is negative. note 2: digital inputs are at rail. fetg is disconnected. sda = scl = v cc . dac1 and m4dac are not loaded. note 3: see the safety shutdown (fetg) output section for details. note 4: eight ranges allow the full-scale range to change from 625mv to 2.5v. note 5: this specification applies to the expected full-scale value for the selected range. see the comp ranging byte for available full-scale ranges. note 6: eight ranges allow the bmd full-scale range to change from 312.5mv to 1.25v. note 7: the output impedance of the ds1865 is proportional to its scale setting. for instance, if using the 1/2 scale, the output impedance would be approximately 1.56k . note 8: this specification applies to the expected full-scale value for the selected range. see the mod ranging byte for available full-scale ranges. note 9: see the apc and quick-trip shared comparator timing section for details. note 10: assuming an appropriate initial step is programmed that would cause the power to exceed the apc set point within four steps, the bias current will be 1% within the time specified by the binary search time. see the bias and mod output during power-up section. note 11: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with the i 2 c stan- dard mode. note 12: c b ? total capacitance of one bus line in picofarads. note 13: eeprom write begins after a stop condition occurs. note 14: guaranteed by design.
ds1865 pon triplexer control and monitoring circuit 6 _____________________________________________________________________ -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 10050 150 200 250 dac1 and m4dac inl ds1865 toc04 dac1 and m4dac position (dec) dac1 and m4dac inl (lsb) -0.05 -0.04 -0.02 -0.03 -0.01 0.01 0 0.02 0.03 0.04 0.05 2.85 3.853.35 4.35 4.85 5.35 dac1 and m4dac offset vs. v cc ds1865 toc05 v cc (v) dac1 and m4dac offset (mv) t a = -40c to +95c load = -0.5ma to +0.5ma -0.012 -0.010 -0.008 -0.004 -0.006 -0.002 0 0.002 -0.5 -0.4 -0.1 -0.3 -0.2 0.10 0.2 0.3 0.4 0.5 dac1 and m4dac offset variation vs. load current ds1865 toc06 load current (ma) dac1 and m4dac offset (mv) v cc = 2.85v v cc = 3.6v v cc = 3.9v 1.245 1.246 1.247 1.248 1.251 1.250 1.249 1.252 1.253 1.254 1.255 -0.5 -0.4 -0.1 -0.3 -0.2 0.10 0.2 0.3 0.4 0.5 dac1 and m4dac output vs. load current ds1865 toc07 load current (ma) dac1 and m4dac output (v) v cc = 2.85v v cc = 3.9v output without offset 0 20 10 40 30 60 50 70 90 80 100 001 010 000 011 100 101 110 111 calculated and desired % change in v mod vs. mod ranging ds1865 toc08 mod ranging value (dec) change in v mod (%) desired value calculated value 0 20 10 40 30 60 50 70 90 80 100 desired and calculated change in v bmd vs. comp ranging ds1865 toc09 comp ranging (dec) change in v bmd (%) 001 010 000 011 100 101 110 111 desired value calculated value typical operating characteristics ( v cc = 3.3v, t a = +25?, unless otherwise noted.) 3.000 4.000 3.500 4.500 5.000 5.500 6.000 6.500 7.000 2.850 3.850 3.350 4.350 4.80 5.350 supply current vs. supply voltage ds1865 toc01 v cc (v) supply current (ma) sda = scl = v cc +95c -40c +25c 3.000 4.000 3.500 4.500 5.000 5.500 6.000 6.500 7.000 -40 0-20 20 40 80 60 supply current vs. temperature ds1865 toc02 temperature (c) supply current (ma) sda = scl = v cc v cc = 3.9v v cc = 2.85v -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 10050 150 200 250 dac1 and m4dac dnl ds1865 toc03 dac1 and m4dac position (dec) dac1 and m4dac dnl (lsb)
ds1865 pon triplexer control and monitoring circuit _____________________________________________________________________ 7 -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1.0 0.5 1.5 2.0 2.5 mon1?mon4 inl ds1865 toc10 mon1?mon4 input voltage (v) mon1?mon4 inl (lsb) using factory-programmed full-scale value of 2.5v -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1.0 0.5 1.5 2.0 2.5 mon1?mon4 dnl ds1865 toc11 mon1?mon4 input voltage (v) mon1?mon4 dnl (lsb) using factory-programmed full-scale value of 2.5v -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 100 50 150 200 250 v bmd inl vs. apc index ds1865 toc12 apc index (dec) v bmd inl (lsb) typical operating characteristics (continued) ( v cc = 3.3v, t a = +25?, unless otherwise noted.) -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 100 50 150 200 250 v mod inl vs. mod index ds1865 toc13 mod index (dec) v mod inl (lsb)
ds1865 pon triplexer control and monitoring circuit 8 _____________________________________________________________________ pin description pin name function 1 ben burst enable input. triggers the sampling of the apc and quick-trip monitors. 2 tx-d transmit disable input. disables bias and mod outputs. 3 tx-f transmit fault output, open drain 4 fetg output to fet gate. signals an external n- or p-channel mosfet to enable/disable the laser? current. 5, 19 v cc supply voltage 6, 18 gnd ground 7, 10, 11, 25 n.c. no connection 8 sda i 2 c serial data. input/output for i 2 c data. 9 scl i 2 c serial clock. input for i 2 c clock. 12?5 mon1?on4 external monitor input 1?. the voltage at these pins are digitized by the internal analog-to-digital converter and can be read through the i 2 c interface. alarm and warning values can be assigned to interrupt the processor based on the adc result. 16 dac1 17 m4dac digital-to-analog output dac1 and m4dac. two 8-bit dac outputs for generating analog voltages. typically used to control the video photodiode bias. m4dac is controlled by the input voltage on mon4 and table 06h lut. 20 bias bias current output. this current dac generates the bias current reference for the max3643. 21 mod modulation output voltage. this 8-bit voltage output has eight full-scale ranges from 1.25v to 0.3125v. this pin is connected to the max3643? vmset input to control the modulation current. 22 bmd monitor diode input (feedback voltage, transmit power monitor) 23 losi loss-of-signal input. this input is accessible in the status register through the i 2 c interface. 24 d0 digital i/o 0. this signal is either the open-drain output driver for losi, or can be controlled by the out0 bit (d0out). the logic level of this pin is indicated by the d0in and los status bits. 26, 27, 28 d1, d2, d3 digital i/o 1?. these are bidirectional pins controlled by internally addressable bits. the outputs are open-drain. ep exposed pad. this contact should be connected to gnd.
ds1865 pon triplexer control and monitoring circuit _____________________________________________________________________ 9 hbias quick- trip limit htxp quick- trip limit ltxp quick- trip limit apc set point from apc lut latch enable v cc temp sensor i 2 c interface sample control 8-bit dac w/scaling digital apc integrator 13-bit dac analog mux mod lut 8-bit dac w/scaling bias max quicktrip interrupt mask interrupt latch interrupt mask interrupt latch power-on analog v cc > v poa nonmaskable interrupt 13-bit adc ds1865 memory organization sram reset digital limit comparator for adc results ds1865 mux mux mux tx-d bmd ben mon3 mon2 mon1 mon4 scl sda ttl losi 0 1 ttl d0 d0 in/los status d0 out mux losi ttl d1 d1 in d1 out ttl d2 d2 in d2 out ttl d3 d3 in d3 out gnd inv losi dac1 8-bit, 2.5v full scale i 2 c programmed nonvolatile setting dac1 fetg bias mod m4dac 8-bit, 2.5v full scale table 06h video power lookup table m4dac i 2 c control v cc v cc eeprom 128 bytes at a0h slave address tx-f table 01h (eeprom) pw1 user memory, alarm trap table 04h (eeprom) modulation lut table 02h (eeprom) configuration and calibration table 05h (eeprom) apc lut table 03h (eeprom) pw2 user memory table 06h (eeprom) m4dac (video gain lut) main memory eeprom/sram adc configuration/results system status bits alarm/warning comparison results/thresholds block diagram
ds1865 pon triplexer control and monitoring circuit 10 ____________________________________________________________________ detailed description the ds1865 integrates the control and monitoring func- tionality required to implement a pon system using maxim? max3643 compact burst-mode laser driver. the compact laser driver solution offers a considerable cost benefit by integrating control and monitoring fea- tures in the low-power cmos process, while leaving only the high-speed portions to the laser driver. key components of the ds1865 are shown in the block diagram and described in subsequent sections. table 1 contains a list of acronyms used in this data sheet. apc control bias current is controlled by an average power control (apc) loop. the apc loop uses digital techniques to overcome the difficulties associated with controlling burst-mode systems. typical operating circuit ben+ ben- dis in- in+ out- bias- bias+ mdin compact burst-mode laser driver ds1865 burst-mode monitor/control circuit mdout out+ v cc tx-f tx-d scl sda losi d1 d2 d0 d3 mon2 mon3 mon4 fetg dac1 m4dac mon1 3.3v thermistor apd boost dc-dc bmd 3.3v vmset modset vref imax gnd biasset benout mod bias ben bcmon vbset transmit power disable input receiver los open-drain los output fault output i 2 c communication receive power additional digital i/o catv 12v ftth catv tia gain control shutdown control max3643 max3654 table 1. acronyms acronym definition adc analog-to-digital converter apc average power control atb alarm trap bytes dac digital-to-analog converter lut lookup table nv nonvolatile pon passive optical network qt quick trip see shadowed eeprom te tracking error txp transmit power
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 11 the apc loop? feedback is the monitor diode (bmd) current, which is converted to a voltage using an exter- nal resistor. the feedback voltage is compared to an 8- bit scaleable voltage reference that determines the apc set point of the system. scaling of the reference voltage accommodates the wide range in photodiode sensitivities. this allows the application to take full advantage of the apc reference? resolution. the ds1865 has an lut to allow the apc set point to change as a function of temperature to compensate for tracking error (te). the te lut (table 05h) has 36 entries that determine the apc setting in 4? windows between -40? to +100?. ranging of the apc dac is possible by programming a single byte in table 02h. modulation control the mod output is an 8-bit scaleable voltage output that interfaces with the max3643? vmset input. an external resistor to ground from the max3643? modset pin sets the maximum current the voltage at vmset input can produce for a given output range. this resistor value should be chosen to produce the maximum modulation current the laser type requires over temperature. then the mod output? scaling is used to calibrate the full- scale (fs) modulation output to a particular laser? requirements. this allows the application to take full advantage of the mod output? resolution. the modula- tion lut can be programmed in 2? increments over the -40? to +102? range. ranging of the mod dac is possible by programming a single byte in table 02h. bias and mod output during power-up on power-up, the modulation and bias outputs remain off until v cc is above v poa and a temperature conver- sion has been completed. if the v cc lo adc alarm is enabled, then a v cc conversion above the customer- defined v cc low alarm level is required before the outputs are enabled with the value determined by the temperature conversion and the modulation lut. when the mod output is enabled and ben is high, the bias output is turned on to a value equal to i step (see figure 1). the startup algorithm checks if this bias cur- rent causes a feedback voltage above the apc set point, and if it does not it continues increasing the bias by i step until the apc set point is exceeded. when the apc set point is exceeded, the ds1865 begins a binary search to quickly reach the bias current corresponding to the proper power level. after the binary search is com- pleted the apc integrator is enabled, and single lsb steps are taken to tightly control the average power. all quick-trip alarm flags are masked until the binary search is completed. however, the bias max alarm is monitored during this time to prevent the bias output from exceeding max ibias. during the bias current ini- tialization, the bias current is not allowed to exceed max ibias. if this occurs during the i step sequence, the binary search routine begins. if max ibias is exceeded during the binary search, the next smaller step is activated. i step or binary increments that would cause i bias to exceed max ibias are not taken. masking the alarms until the completion of the binary search prevents false trips during startup. i step is programmed by the customer using the startup step register. this value should be programmed to the maximum safe current increase that is allowable during startup. if this value is programmed too low, the ds1865 will still operate, but it could take significantly longer for the algorithm to converge and hence to control the aver- age power. if a fault is detected and tx-d is toggled to re-enable the outputs, the ds1865 powers up following a similar sequence to an initial power-up. the only difference is that the ds1865 already has determined the present tem- perature, so the t init time is not required for the ds1865 to recall the apc and mod set points from eeprom. if the bias-en bit (table 02h, register 80h) is written to 0, the bias dac is manually controlled by the man ibias register (table 02h, registers f8h?9h). bias and mod output as a function of transmit disable (tx-d) if the tx-d pin is asserted (logic 1) during normal oper- ation, the outputs are disabled within t off . when tx-d is deasserted (logic 0), the ds1865 turns on the mod output with the value associated with the present tem- perature, and initializes the bias using the same search algorithm used at startup. when asserted, the soft tx-d (lower memory, register 6eh) offers a soft- ware control identical to the tx-d pin (see figure 2). apc and quick-trip shared comparator timing as shown in figure 3, the ds1865? input comparator is shared between the apc control loop and the three quick-trip alarms (txp-hi, txp-lo, and bias hi). the comparator polls the alarms in a round-robin multi- plexed sequence. six of every eight comparator read- ings are used for apc loop-bias current control. the other two updates are used to check the htxp/ltxp (monitor diode voltage) and the hbias (mon1) signals against the internal apc and bias reference. the htxp/ltxp comparison checks htxp to see if the last
ds1865 pon triplexer control and monitoring circuit 12 ____________________________________________________________________ bias update comparison was above the apc set point, and checks ltxp to see if the last bias update compari- son was below the apc set point. depending on the results of the comparison, the corresponding alarms and warnings (txp-hi, txp-lo) are asserted or deasserted. the ds1865 has a programmable comparator sample time based on an internally generated clock to facilitate a wide variety of external filtering options suitable for burst-mode transmitter data rates between 155mbps and 1250mbps. the rising edge of the burst enable (ben) triggers the sample to occur, and the update rate register (table 02h, register 88h) determines the sam- pling time. the first sample occurs t first after the rising edge of ben. the internal clock is asynchronous to ben, causing a ?0ns uncertainty regarding when the first sample will occur following ben. after the first sample occurs, subsequent samples occur on a regular interval, t rep . table 2 shows the sample rate options available. 1 2 3 4 5 6 7 8 9 10 11 12 13 t init v poa binary search apc integrator on t search v mod i bias v cc bias sample i step 4x i step 3x i step 2x i step figure 1. power-up timing tx-d i bias v mod t off t on t on t off figure 2. tx-d timing (normal operating conditions) table 2. update rate timing sr 3 ?r 0 minimum time from ben to first sample (t first ) ?0ns repeated sample period following first sample (t rep ) 0000b 350ns 800ns 0001b 550ns 1200ns 0010b 750ns 1600ns 0011b 950ns 2000ns 0100b 1350ns 2800ns 0101b 1550ns 3200ns 0110b 1750ns 3600ns 0111b 2150ns 4400ns 1000b 2950ns 6000ns 1001b* 3150ns 6400ns * all codes greater than 1001b (1010b?111b) use the maximum sample time of code 1001b.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 13 updates to the txp-hi, txp-lo, and bias hi quick-trip alarms do not occur during the burst-enable low time. any quick-trip alarm that is detected by default remains active until a subsequent comparator sample shows the condition no longer exists. a second bias-current monitor (bias max) compares the ds1865? bias dac? code to a digital value stored in the max ibias register. this comparison is made every bias-current update to ensure that a high bias current is quickly detected. monitors and fault detection monitors monitoring functions on the ds1865 include four quick- trip comparators and six adc channels. this monitor- ing, combined with the interrupt masks, determines when/if the ds1865 shuts down its outputs and triggers the tx-f and fetg outputs. all the monitoring levels and interrupt masks are user programmable. four quick-trip monitors and alarms four quick-trip monitors are provided to detect potential laser safety issues. these monitor: 1) high bias current (hbias) 2) low transmit power (ltxp) 3) high transmit power (htxp) 4) max output current (max ibias) the high and low transmit power quick-trip registers (htxp and ltxp) set the thresholds used to compare against the bmd voltage to determine if the transmit power is within specification. the hbias quick-trip com- pares the mon1 input (generally from the max3643 bias monitor output) against its threshold setting to determine if the present bias current is above specifica- tion. the bias max quick-trip is a digital comparison that determines if the bias dac indicates that the bias current is above specification. i bias is not allowed to exceed the value set in the max ibias register. when the ds1865 detects that the bias is at the limit, it sets the bias max status bit and holds the bias current at the max ibias level. the quick-trips are routed to the tx-f and fetg outputs through interrupt masks to allow com- binations of these alarms to be used to trigger these out- puts. when fetg is triggered, the ds1865 also disables the mod and bias outputs. see the bias and mod output during power-up section for details. six adc monitors and alarms the adc monitors six channels that measure tempera- ture (internal temp sensor), v cc , mon1, mon2, mon3, and mon4 using an analog multiplexer to measure them round-robin with a single adc. each channel has a customer-programmable full-scale range and offset value that is factory programmed to a default value (see table 3). additionally, mon1?on4 can right shift results by up to 7 bits before the results are compared to alarm thresholds or read over the i 2 c bus. this allows customers with specified adc ranges to cali- brate the adc full scale to a factor of 1/2 n of their spec- ified range to measure small signals. the ds1865 can then right shift the results by n bits to maintain the bit weight of their specification. last burst's bias sample ben bias dac code quick-trip sample times hbias sample t first t rep htxp/ltxp sample bias sample bias sample bias sample bias sample bias sample bias sample bias sample figure 3. apc and quick-trip alarm sample timing table 3. adc default monitor full-scale ranges signal (units) +fs signal +fs hex -fs signal -fs hex temperature ( o c) 127.996 7fff -128 8000 v cc (v) 6.5528 fff8 0v 0000 mon1?on4 (v) 2.4997 fff8 0v 0000
ds1865 pon triplexer control and monitoring circuit 14 ____________________________________________________________________ the adc results (after right shifting, if used) are com- pared to high alarm thresholds, low alarm thresholds, and the warning threshold after each conversion, and the corresponding alarms are set, which can be used to trigger the tx-f or fetg outputs. these adc thresh- olds are user programmable, as are the masking regis- ters that can be used to prevent the alarms from triggering the tx-f and fetg outputs. adc timing there are six analog channels that are digitized in a round-robin fashion in the order as shown in figure 4. the total time required to convert all six channels is t rr (see timing characteristics (control loop and quick-trip) for details). right shifting adc result if the weighting of the adc digital reading must con- form to a predetermined full-scale value defined by a standard? specification, then right shifting can be used to adjust the predetermined full-scale analog measure- ment range while maintaining the weighting of the adc results. the ds1865? range is wide enough to cover all requirements; when the maximum input value is far short of the fs value, right shifting can be used to obtain greater accuracy. for instance, the maximum voltage might be 1/8th the specified predetermined full- scale value, so only 1/8th the converter? range is used. an alternative is to calibrate the adc? full-scale range to 1/8th the readable predetermined full-scale value and use a right-shift value of 3. with this implementa- tion, the resolution of the measurement is increased by a factor of 8, and because the result is digitally divided by 8 by right shifting, the bit weight of the measurement still meets the standard? specification (i.e., sff-8472). the right-shift operation on the adc result is carried out based on the contents of right shift control registers (table 02h, registers 8eh-8fh) in eeprom. four ana- log channels, mon1?on4, each have 3 bits allocated to set the number of right shifts. up to 7 right-shift oper- ations are allowed and are executed as a part of every conversion before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers (table 01h, registers 62h?bh). this is true during the setup of internal cali- bration as well as during subsequent data conversions. transmit fault (tx-f) output the tx-f output has masking registers for the six adc alarms and the four qt alarms to select which compar- isons cause it to assert. in addition, the fetg alarm is selectable through the tx-f mask to cause tx-f to assert. all alarms, with the exception of fetg, only cause tx-f to remain active while the alarm condition persists. however, the tx-f latch bit can enable the tx-f output to remain active until it is cleared by the tx-f reset bit, tx-d, soft tx-d, or by power cycling the part. if the fetg output is configured to trigger tx-f, it indicates that the ds1865 is in shutdown, and requires tx-d, soft tx-d, or cycling power to reset. the qt alarms are masked until the completion of the binary search. only enabled alarms will activate tx-f. see figure 5. table 4 shows tx-f as a function of tx-d and the alarm sources. safety shutdown (fetg) output the fetg output has masking registers (separate from tx-f) for the five adc alarms and the four qt alarms to select which comparisons cause it to assert. unlike tx-f, the fetg output is always latched in case it is triggered by an unmasked alarm condition. its output polarity is programmable to allow an external nmosfet or pmosfet to open during alarms to shut off the laser diode current. if the fetg output triggers, indicating that the ds1865 is in shutdown, it requires tx-d, soft tx-d, or cycling power to be reset. under all conditions, when the analog outputs are reinitialized after being disabled, all the alarms with the exception of the v cc low adc alarm are cleared. the v cc low alarm must remain active to prevent the output from attempting to operate when temp vcc mon1 mon2 mon3 mon4 temp vcc one round-robin adc cycle mon4 t rr note: at power-up, if the v cc low alarm is set for either the tx-f or fetg output, the adc round-robin timing cycles between temp and v cc only until v cc is above the v cc low threshold. figure 4. adc round-robin timing
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 15 inadequate v cc exists to operate the laser driver. once adequate v cc is present to clear the v cc low alarm, the outputs are enabled following the same sequence as the power-up sequence. as previously mentioned, the fetg is an output used to disable the laser current through a series nmosfet or pmosfet. this requires that the fetg output can sink or source current. because the ds1865 does not know if it should sink or source current before v cc exceeds v poa , which triggers the ee recall, this output will be high impedance when v cc is below v poa (see the low-voltage operation section for details and diagram). the application circuit must use a pullup or pulldown resistor on this pin that pulls fetg to the alarm/shutdown state (high for a pmos, low for a nmos). once v cc is above v poa , the ds1865 pulls the fetg output to the state determined by the fetg dir bit (table 02h, register 89h). fetg dir is 0 if an nmos is used and 1 if a pmos is used. determining alarm causes using the i 2 c interface to determine the cause of the tx-f or fetg alarm, the system processor can read the ds1865? alarm trap bytes (atb) through the i 2 c interface (in table 01h). the atb has a bit for each alarm. any time an alarm occurs, regardless of the mask bit? state, the ds1865 sets the corresponding bit in the atb. active atb bits remain set until written to zeros through the i 2 c interface. on power- up, the atb is zeros until alarms dictate otherwise. die identification the ds1865 has an id hard coded to its die. two regis- ters (table 02h bytes 86h?7h) are assigned for this feature. byte 86h reads 65h to identify the part as the ds1865, byte 87h reads the die revision. low-voltage operation the ds1865 contains two power-on reset (por) levels. the lower level is a digital por (v pod ) and the higher level is an analog por (v poa ). at startup, before the supply voltage rises above v poa , the outputs are dis- abled (fetg and bias outputs are high impedance, mod is low), all sram locations are low (including shadowed eeprom), and all analog circuitry is dis- abled. when v cc reaches v poa , the see is recalled, and the analog circuitry is enabled. while v cc remains above v poa , the device is in its normal operating state, and it responds based on its nonvolatile configuration. if during operation v cc falls below v poa but is still above v pod , the sram retains the see settings from tx-f latched operation tx-f non latched operation detection of tx-f fault tx-d or tx-f reset tx-f detection of tx-f fault tx-f figure 5. tx-f timing table 4. tx-f as a function of tx-d and alarm sources v cc > v poa tx-d nonmasked tx-f alarm tx-f no x x 1 yes 0 0 0 yes 0 1 1 yes 1 x 0
ds1865 pon triplexer control and monitoring circuit 16 ____________________________________________________________________ the first see recall, but the device analog is shut down and the outputs are disabled. fetg is driven to its alarm state defined by the fetg dir bit (table 02h, register 89h). if the supply voltage recovers back above v poa , the device immediately resumes normal functioning. if the supply voltage falls below v pod , the device sram is placed in its default state and another see recall is required to reload the nonvolatile settings. the eeprom recall occurs the next time v cc exceeds v poa . figure 7 shows the sequence of events as the voltage varies. any time v cc is above v pod , the i 2 c interface can be used to determine if v cc is below the v poa level. this is accomplished by checking the rdyb bit in the status (lower memory, register 6eh) byte. rdyb is set when v cc is below v poa . when v cc rises above v poa , rdyb is timed (within 500?) to go to 0, at which point the part is fully functional. for all device addresses sourced from eeprom (table 02h, register 8ch), the default device address is a2h until v cc exceeds v poa allowing the device address to be recalled from the eeprom. power-on analog (poa) poa holds the ds1865 in reset until v cc is at a suitable level (v cc > v poa ) for the part to accurately measure with its adc and compare analog signals with its quick- trip monitors. because v cc cannot be measured by the adc when v cc is less than v poa , poa also asserts the v cc low alarm, which is cleared by a v cc adc conver- sion greater than the customer-programmable v cc low adc limit. this prevents the tx-f and fetg outputs from glitching during a slow power-up. the tx-f and fetg outputs do not latch until there is a conversion above v cc low limit. the poa alarm is nonmaskable. the tx-f and fetg outputs are asserted when v cc is below v poa . see the low-voltage operation section for more information. dac1 output the dac1 output has a 0 to 2.5v range, 8 bits of resolu- tion, and is programmed through the i 2 c interface. the dac1 setting is nonvolatile and password 2 (pw2) pro- tected. m4dac output the m4dac output has a 0 to 2.5v range, 8 bits of res- olution, and is controlled by an lut indexed by the mon4 voltage. the m4dac lut (table 06h) is non- volatile and pw2 protected. see the memory organization section for details. i bias v mod detection of fetg fault t off t on t on t off tx-d t fetg:on fetg* *fetg dir = 0 t fetg:off figure 6. fetg/modulation and bias timing (fault condition detected) table 5. fetg, mod, and bias outputs as a function of tx-d and alarm sources v cc > v poa tx-d nonmasked fetg alarm fetg mod and bias outputs yes 0 0 fetg dir enabled yes 0 1 fetg dir disabled yes 1 x fetg dir disabled
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 17 digital i/o pins five digital i/o pins are provided for additional monitor- ing and control of the triplexer. by default the losi pin is used to convert a standard comparator output for loss of signal (losi) to an open-collector output. this means the mux shown on the block diagram by default selects the losi pin as the source for the d0 output transistor. the level of the d0 pin can be read in the status byte (lower memory, register 6eh) as the los status bit. the los status bit reports back the logic level of the d0 pin, so an external pullup resistor must be provided for this pin to output a high level. the losi signal can be inverted before driving the open-drain output transistor using the xor gate provided. the mux losi allows the d0 pin to be used identically to the d1, d2, and d3 pins. however, the mux setting (stored in the eeprom) does not take effect until v cc > v poa , allowing the eeprom to recall. this requires the losi pin to be grounded for d0 to act identical to the d1, d2, and d3 pins. digital pins d1, d2, and d3 can be used as inputs or outputs. external pullup resistors must be provided to realize high logic levels. the levels of these input pins can be read by reading the din byte (lower memory, register 79h), and the open-drain outputs can be con- trolled using the dout byte (lower memory, register 78h). when v cc < v poa , these outputs are high imped- ance. once v cc v poa , the outputs go to the power-on default state stored in the dpu byte (table 02h, register c0h). the eeprom determined default state of the pin can be modified with pw2 access. after the default state has been recalled, the sram registers controlling out- puts can be modified without password access. this allows the outputs to be used to control serial interfaces without wearing out the default eeprom setting. memory organization the ds1865 features eight banks of memory composed of the following. the lower memory is addressed from 00h to 7fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (pwe), and the table select byte. the table select byte determines which table (01h?6h) will be mapped into the upper memory locations, namely 80h?fh (unless stated otherwise). table 01h primarily contains user eeprom (with pw1 level access) as well as some alarm and warn- ing status bytes. table 02h is a multifunction space that contains configuration registers, scaling and offset values, passwords, interrupt registers, as well as other mis- cellaneous control bytes. table 03h is strictly user eeprom that is protected by a pw2 level access. table 04h contains a temperature-indexed lut for control of the modulation voltage. the modulation lut can be programmed in 2? increments over the -40? to +102? range. this register is protected by a pw2 level access. table 05h contains another lut, which allows the apc set point to change as a function of tempera- ture to compensate for tracking error (te). this te lut has 36 entries that determine the apc setting in 4? windows between -40? to +100?. this reg- ister is protected by a pw2 level access. v cc v poa v pod fetg see* *see = shadowed eeprom high impedance high impedance high impedance normal operation driven to fetg dir normal operation precharged to 0 precharged to 0 precharged to 0 recalled value recalled value driven to fetg dir normal operation driven to fetg dir see recall see recall figure 7. low-voltage hysteresis example
ds1865 pon triplexer control and monitoring circuit 18 ____________________________________________________________________ table 06h contains a mon4-indexed lut for con- trol of the m4dac voltage. the m4dac lut has 32 entries that are configurable to act as one 32-entry lut or two 16-entry luts. when configured as one 32-byte lut, each entry corresponds to an incre- ment of 1/32 of the full scale. when configured as two 16-byte luts, the first 16 bytes and the last 16 bytes each correspond to 1/16 of full scale. either of the two sections is selected with a separate con- figuration bit. this lut is protected by a pw2 level access. auxiliary memory is eeprom accessible at the i 2 c slave address, a0h. see the register map tables for a more complete detail of each byte? function, as well as for read/write permis- sions for each byte. shadowed eeprom in addition to volatile memory (sram) and nonvolatile memory (eeprom), the ds1865 also features shadowed eeprom. shadowed eeprom (see) can be configured as either volatile or nonvolatile memory using the seeb bit in table 02h, register 80h. the ds1865 uses shadowed eeprom memory for key memory addresses that can be rewritten many times. by default the shadowed eeprom bit, seeb, is not set and these locations act as ordinary eeprom. by setting seeb, these locations function like sram cells, which allow an infinite number of write cycles without concern of wearing out the eeprom. this also eliminates the requirement for the eeprom write time, t wr . because changes made with seeb enabled do not affect the eeprom, these changes are not retained through power cycles. the power-up value is the last value writ- ten with seeb disabled. this function can be used to limit the number of eeprom writes during calibration or to change the monitor thresholds periodically during nor- mal operation, helping to reduce the number of times eeprom is written. the memory organization descrip- tion indicates which locations are shadowed eeprom. atb misc. control bits eeprom 7fh i 2 c slave address a0h 00h ffh 80h f8h pw1 level access eeprom (120 bytes) table 01h auxillary memory table select byte password entry (pwe) (4 bytes) digital diagnostic functions 7fh i 2 c slave address a2h (default) 00h lower memory ffh f7h c7h f7h 80h f8h c8h configuration and control no memory table 02h ffh 80h pw2 level access eeprom (128 bytes) table 03h c7h 80h modulation lut table 04h a7h 80h apc lut table 05h 9fh 80h m4dac lut table 06h dec 0 hex 0 127 7f 128 80 255 ff figure 8. memory map
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 19 i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle, it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 9 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 9 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data trans- fer to indicate that it will immediately initiate a new data transfer following the current one. repeated start conditions are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identi- cally to a normal start condition. see figure 9 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold-time requirements (figure 9). data is shift- ed into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock puls- es including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmit- ting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is prop- erly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte (figure 9) sent immediately following a start condition. the slave address byte contains the slave address in the most sig- nificant 7 bits and the r/ w bit in the least significant bit. the ds1865 responds to two slave addresses. the auxil- iary memory always responds to a fixed i 2 c slave address, a0h. the lower memory and tables 01h?6h respond to i 2 c slave addresses that can be configured to any value between 00h?eh using the device address byte (table 02h, register 8ch). the user also must set the asel bit (table 02h, register 89h) for this address to be active. by writing the correct slave address with r/ w = 0, the master indicates it will write data to the slave. if r/ w = 1, the mas- ter reads data from the slave. if an incorrect slave address is written, the ds1865 assumes the master is communicat- ing with another i 2 c device and ignores the communica- tions until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte.
ds1865 pon triplexer control and monitoring circuit 20 ____________________________________________________________________ i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the i 2 c slave address byte (r/ w = 0), write the byte of data, and generate a stop condition. the master must read the slave? acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condi- tion, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and gener- ates a stop condition. the ds1865 writes 1 to 8 bytes (1 page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages result in the address counter wrapping around to the beginning of the present row. example: a 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three ?onsecutive?addresses. the result is that addresses 06h and 07h contain 11h and 22h, respectively, and the third data byte, 33h, is written to address 00h. to prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the page, then wait for the bus-free or eeprom-write time to elapse. then the master can generate a new start condition, and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time an eeprom location is written, the ds1865 requires the eeprom write time (t w ) after the stop condition to write the contents of the byte of data to eeprom. during the eeprom write time, the device does not acknowledge its slave address because it is busy. it is possible to take advan- tage of that phenomenon by repeatedly addressing the ds1865, which allows the next page to be written as soon as the ds1865 is ready to receive the data. the alternative to acknowledge polling is to wait for a maxi- mum period of t w to elapse before attempting to write again to the ds1865. eeprom write cycles: when eeprom writes occur to the memory, the ds1865 writes to all three eeprom memory locations, even if only a single byte was modi- fied. because all three bytes are written, the bytes that were not modified during the write transaction are still subject to a write cycle. this can result in all three bytes being worn out over time by writing a single byte repeatedly. the ds1865? eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case tem- perature. it can handle approximately 10 times that many writes at room temperature. writing to sram- shadowed eeprom memory with seeb = 1 does not count as an eeprom write cycle when evaluating the eeprom? estimated lifetime. sda scl t hd:sta t low t high t r t f t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start t buf note: timing is referenced to v il(max) and v ih(min) . figure 9. i 2 c timing diagram
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 21 reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address pointer to a particular value. to do this, the master gen- erates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition.
ds1865 pon triplexer control and monitoring circuit 22 ____________________________________________________________________ lower memory word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <1> threshold 0 temp alarm hi temp alarm lo temp warn hi temp warn lo 08 <1> threshold 1 v cc alarm hi v cc alarm lo v cc warn hi v cc warn lo 10 <1> threshold 2 mon1 alarm hi mon1 alarm lo mon1 warn hi mon1 warn lo 18 <1> threshold 3 mon2 alarm hi mon2 alarm lo mon2 warn hi mon2 warn lo 20 <1> threshold 4 mon3 alarm hi mon3 alarm lo mon3 warn hi mon3 warn lo 28 <1> threshold 5 mon4 alarm hi mon4 alarm lo mon4 warn hi mon4 warn lo 30 <1> pw2 ee ee ee ee ee ee ee ee ee 38 <1> pw2 ee ee ee ee ee ee ee ee ee 40 <1> pw2 ee ee ee ee ee ee ee ee ee 48 <1> pw2 ee ee ee ee ee ee ee ee ee 50 <1> pw2 ee ee ee ee ee ee ee ee ee 58 <1> pw2 ee ee ee ee ee ee ee ee ee 60 <2> adc values 0 temp value v cc value mon1 value mon2 value 68 <0> adc values 1 <2> mon3 value <2> mon4 value <2> reserved <0> status <3> update 70 <2> alarm/warn alarm 3 alarm 2 alarm 1 alarm 0 warn 3 warn 2 reserved 78 <0> table select <2> dout <2> din <6> reserved <6> pwe msb <6> pwe lsb <5> tbl sel access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and ds1865 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 lower memory register map this register map shows each byte/word in terms of the row it is on in the memory. the first byte in the row is located in memory at the hexadecimal row address in the left-most column. each subsequent byte on the row is one/two memory locations beyond the previous byte/word? address. a total of 8 bytes are present on each row. for more information about each of these bytes, see the corresponding register description in the following tables. register maps
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 23 table 01h register map table 01h (pw1) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <7> pw1 ee ee ee ee ee ee ee ee ee 88 <7> pw1 ee ee ee ee ee ee ee ee ee 90 <7> pw1 ee ee ee ee ee ee ee ee ee 98 <7> pw1 ee ee ee ee ee ee ee ee ee a0 <7> pw1 ee ee ee ee ee ee ee ee ee a8 <7> pw1 ee ee ee ee ee ee ee ee ee b0 <7> pw1 ee ee ee ee ee ee ee ee ee b8 <7> pw1 ee ee ee ee ee ee ee ee ee c0 <7> pw1 ee ee ee ee ee ee ee ee ee c8 <7> pw1 ee ee ee ee ee ee ee ee ee d0 <7> pw1 ee ee ee ee ee ee ee ee ee d8 <7> pw1 ee ee ee ee ee ee ee ee ee e0 <7> pw1 ee ee ee ee ee ee ee ee ee e8 <7> pw1 ee ee ee ee ee ee ee ee ee f0 <7> pw1 ee ee ee ee ee ee ee ee ee f8 <11> alarm trap alarm 3 alarm 2 alarm 1 alarm 0 warn 3 warn 2 reserved access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and ds1865 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
ds1865 pon triplexer control and monitoring circuit 24 ____________________________________________________________________ table 02h register map table 02h (pw2) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <0> config 0 <8> mode <4> t index <4> mod dac <4> apc dac <4> v index <4> m4dac <10> d ev ic e id <10> device ver 88 <8> config 1 update rate config startup step mod ranging device address comp ranging rshift 1 rshift 0 90 <8> scale 0 reserved v cc scale mon1 scale mon2 scale 98 <8> scale 1 mon3 scale mon4 scale reserved reserved a0 <8> offset 0 reserved v cc offset mon1 offset mon2 offset a8 <8> offset 1 mon3 offset mon4 offset reserved internal temp offset * b0 <9> p wd v alu e pw1 msw pw1 lsw pw2 msw pw2 lsw b8 <8> interrupt fetg en 1 fetg en 0 tx-f en 1 tx-f en 0 htxp ltxp hbias max ibias c0 <8> cntl out dpu reserved reserved reserved dac1 reserved reserved m 4 lu t c n tl c8-f7 empty empty empty empty empty empty empty empty empty f8 <0> m an ibias <4> m an ibias 1 <4> m an ibias 0 <4> m an _c ntl <10> bias dac 1 <10> bias dac 0 re se rv ed re se rv ed re se rv ed access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and ds1865 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 * the final result must be xored with bb40h before writing to this register.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 25 table 03h register map table 03h (pw3) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> pw2 ee ee ee ee ee ee ee ee ee 88 <8> pw2 ee ee ee ee ee ee ee ee ee 90 <8> pw2 ee ee ee ee ee ee ee ee ee 98 <8> pw2 ee ee ee ee ee ee ee ee ee a0 <8> pw2 ee ee ee ee ee ee ee ee ee a8 <8> pw2 ee ee ee ee ee ee ee ee ee b0 <8> pw2 ee ee ee ee ee ee ee ee ee b8 <8> pw2 ee ee ee ee ee ee ee ee ee c0 <8> pw2 ee ee ee ee ee ee ee ee ee c8 <8> pw2 ee ee ee ee ee ee ee ee ee d0 <8> pw2 ee ee ee ee ee ee ee ee ee d8 <8> pw2 ee ee ee ee ee ee ee ee ee e0 <8> pw2 ee ee ee ee ee ee ee ee ee e8 <8> pw2 ee ee ee ee ee ee ee ee ee f0 <8> pw2 ee ee ee ee ee ee ee ee ee f8 <8> pw2 ee ee ee ee ee ee ee ee ee access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and ds1865 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
ds1865 pon triplexer control and monitoring circuit 26 ____________________________________________________________________ table 04h register map table 04h (mod lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut4 mod mod mod mod mod mod mod mod 88 <8> lut4 mod mod mod mod mod mod mod mod 90 <8> lut4 mod mod mod mod mod mod mod mod 98 <8> lut4 mod mod mod mod mod mod mod mod a0 <8> lut4 mod mod mod mod mod mod mod mod a8 <8> lut4 mod mod mod mod mod mod mod mod b0 <8> lut4 mod mod mod mod mod mod mod mod b8 <8> lut4 mod mod mod mod mod mod mod mod c0 <8> lut4 mod mod mod mod mod mod mod mod access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and ds1865 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 05h register map table 05h (apc lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 88 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 90 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 98 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref a0 <8> lut5 apc ref apc ref apc ref apc ref re se rv ed re se rv ed re se rv ed re se rv ed access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and ds1865 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 27 table 06h register map table 06h (lut for m4dac) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut6 m4dac m4dac m4dac m4dac m4dac m4dac m4dac m4dac 88 <8> lut6 m4dac m4dac m4dac m4dac m4dac m4dac m4dac m4dac 90 <8> lut6 m4dac m4dac m4dac m4dac m4dac m4dac m4dac m4dac 98 <8> lut6 m4dac m4dac m4dac m4dac m4dac m4dac m4dac m4dac access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and ds1865 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
ds1865 pon triplexer control and monitoring circuit 28 ____________________________________________________________________ aux a0h memory register map aux memory (a0h) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <5> aux ee ee ee ee ee ee ee ee ee 08 <5> aux ee ee ee ee ee ee ee ee ee 10 <5> aux ee ee ee ee ee ee ee ee ee 18 <5> aux ee ee ee ee ee ee ee ee ee 20 <5> aux ee ee ee ee ee ee ee ee ee 28 <5> aux ee ee ee ee ee ee ee ee ee 30 <5> aux ee ee ee ee ee ee ee ee ee 38 <5> aux ee ee ee ee ee ee ee ee ee 40 <5> aux ee ee ee ee ee ee ee ee ee 48 <5> aux ee ee ee ee ee ee ee ee ee 50 <5> aux ee ee ee ee ee ee ee ee ee 58 <5> aux ee ee ee ee ee ee ee ee ee 60 <5> aux ee ee ee ee ee ee ee ee ee 68 <5> aux ee ee ee ee ee ee ee ee ee 70 <5> aux ee ee ee ee ee ee ee ee ee 78 <5> aux ee ee ee ee ee ee ee ee ee access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and ds1865 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 springer
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 29 lower memory, register 00h to 01h: temp alarm hi lower memory, register 04h to 05h: temp warn hi factory default: 7fffh read access all write access pw2 memory type: nonvolatile (see) 00h, 04h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 01h, 05h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurement updates above this two? complement threshold will set its corresponding alarm or warning bit. temperature measurement updates equal to or below this threshold will clear its alarm or warning bit. lower memory, register 02h to 03h: temp alarm lo lower memory, register 06h to 07h: temp warn lo factory default: 8000h read access all write access pw2 memory type: nonvolatile (see) 02h, 06h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h, 07h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurement updates above this two? complement threshold will set its corresponding alarm or warning bit. temperature measurement updates equal to or below this threshold will clear its alarm or warning bit. lower memory registers
ds1865 pon triplexer control and monitoring circuit 30 ____________________________________________________________________ lower memory, register 08h to 09h: v cc alarm hi lower memory, register 0ch to 0dh: v cc warn hi lower memory, register 10h to 11h: mon1 alarm hi lower memory, register 14h to 15h: mon1 warn hi lower memory, register 18h to 19h: mon2 alarm hi lower memory, register 1ch to 1dh: mon2 warn hi lower memory, register 20h to 21h: mon3 alarm hi lower memory, register 24h to 25h: mon3 warn hi lower memory, register 28h to 29h: mon4 alarm hi lower memory, register 2ch to 2dh: mon4 warn hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 08, 0c, 10, 14, 18, 1c, 20, 24, 28, 2ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 09, 0d, 11, 15, 19, 1d, 21, 25, 29, 2dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurement updates above this unsigned threshold will set its corresponding alarm or warning bit. voltage measurements equal to or below this threshold will clear its alarm or warning bit.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 31 lower memory, register 30h to 5fh: pw2 ee factory default: 00h read access all write access pw2 memory type: nonvolatile (ee) 30h to 5fh ee ee ee ee ee ee ee ee bit7 bit0 pw2 level access controlled eeprom. lower memory, register 0ah to 0bh: v cc alarm lo lower memory, register 0eh to 0fh: v cc warn lo lower memory, register 12h to 13h: mon1 alarm lo lower memory, register 16h to 17h: mon1 warn lo lower memory, register 1ah to 1bh: mon2 alarm lo lower memory, register 1eh to 1fh: mon2 warn lo lower memory, register 22h to 23h: mon3 alarm lo lower memory, register 26h to 27h: mon3 warn lo lower memory, register 2ah to 2bh: mon4 alarm lo lower memory, register 2eh to 2fh: mon4 warn lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 0a, 0e, 12, 16, 1a, 1e, 22, 26, 2a, 2eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0b, 0f, 13, 17, 1b, 1f, 23, 27, 2b, 2fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurement updates above this unsigned threshold will set its corresponding alarm or warning bit. voltage measurements equal to or below this threshold will clear its alarm or warning bit.
ds1865 pon triplexer control and monitoring circuit 32 ____________________________________________________________________ lower memory, register 60h to 61h: temp value power-on value 0000h read access all write access n/a memory type: volatile 60h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 61h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 signed two? complement direct-to-temperature measurement. lower memory, register 6ch to 6d: reserved power-on value 00h read access all write access n/a memory type: 6c, 6dh 000000000 bit7 bit0 these registers are reserved. the value when read is 00h. lower memory, register 62h to 63h: v cc value lower memory, register 64h to 65h: mon1 value lower memory, register 66h to 67h: mon2 value lower memory, register 68h to 69h: mon3 value lower memory, register 6ah to 6bh: mon4 value power-on value 0000h read access all write access n/a memory type: volatile 62, 64, 66, 68, 6ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 63, 65, 67, 69, 6bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 left-justified unsigned voltage measurement.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 33 lower memory, register 6eh: status power-on value x000 0x0x b read access all write access see below memory type: volatile w r i te access n/a all n/a all all n/a n/a n/a 6eh fetg status soft fetg reserved tx-f reset soft tx-d tx-f status los status rdyb bit7 bit0 bit7 fetg status: reflects the active state of fetg. the fetg-dir bit in table 02h, register 89h defines the polarity of fetg. 0 = normal operation. bias and modulation outputs are enabled. 1 = the fetg output is active. bias and modulation outputs are disabled. bit6 soft fetg: 0 = (default) 1 = forces the bias and modulation outputs to their off states and asserts the fetg output. bit5 reserved (default = 0) bit4 tx-f reset: 0 = does not affect the tx-f output. (default) 1 = resets the latch for the tx-f output. this bit is self-clearing after the reset. bit3 soft tx-d: this bit allows a software control is identical to the tx-d pin. see the section on tx-d for further information. its value is wired-ored with the logic value of the tx-d pin. 0 = internal tx-d signal is equal to external tx-d pin. 1 = internal tx-d signal is high. bit2 tx-f status: reflects the active state of tx-f. 0 = tx-f pin is not active. 1 = tx-f pin is active. bit1 los status: loss of signal. reflects the logic level of the d0 input pin. note that with the use of the mux losi and inv losi bits (table 02h, register c0h), the d0 pin is controlled by the losi pin. 0 = d0 is logic-low. 1 = d0 is logic-high. bit0 rdyb: ready bar. 0 = v cc is above poa. 1 = v cc is below poa or too low to communicate over the i 2 c bus.
ds1865 pon triplexer control and monitoring circuit 34 ____________________________________________________________________ lower memory, register 6fh: update power-on value 00h read access all write access all + ds1865 hardware memory type: volatile 6fh temp rdy v cc rdy mon1 rdy mon2 rdy mon3 rdy mon4 rdy reserved reserved bit7 bit0 update of completed conversions. at power-on, these bits are cleared and are set as each conversion is completed. these bits can be cleared so that a completion of a new conversion is verified.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 35 lower memory, register 70h: alarm 3 power-on value 10h read access all write access n/a memory type: volatile 70h temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo bit7 bit0 bit7 temp hi: high alarm status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit6 temp lo: low alarm status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit5 v cc hi: high alarm status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit4 v cc lo: low alarm status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it will clear itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit3 mon1 hi: high alarm status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit2 mon1 lo: low alarm status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit1 mon2 hi: high alarm status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit0 mon2 lo: low alarm status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting.
ds1865 pon triplexer control and monitoring circuit 36 ____________________________________________________________________ lower memory, register 71h: alarm 2 power-on value 00h read access all write access n/a memory type: volatile 71h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit7 bit0 bit7 mon3 hi: high alarm status for mon3 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit6 mon3 lo: low alarm status for mon3 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit5 mon4 hi: high alarm status for mon4 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit4 mon4 lo: low alarm status for mon4 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit3:0 reserved lower memory, register 72h: alarm 1 power-on value 00h read access all write access n/a memory type: volatile 72h reserved reserved reserved reserved bias hi reserved txp hi txp lo bit7 bit0 bit7:4 reserved bit3 bias hi: high alarm status bias; fast comparison. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit2 reserved bit1 txp hi: high alarm status tx-p; fast comparison. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit0 txp lo: low alarm status tx-p; fast comparison. 0 = (default) last comparison was above threshold setting. 1 = last comparison was below threshold setting.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 37 lower memory, register 73h: alarm 0 power-on value 00h read access all write access n/a memory type: volatile 73h reserved reserved reserved reserved bias max reserved reserved reserved bit7 bit0 bit7:4 reserved bit3 bias max: alarm status for maximum digital setting of i bias . 0 = (default) the value for i bias is equal to or below the max ibias setting. 1 = requested value for i bias is greater than the max ibias setting. bit2:0 reserved
ds1865 pon triplexer control and monitoring circuit 38 ____________________________________________________________________ lower memory, register 74h: warn 3 power-on value 10h read access all write access n/a memory type: volatile 74h temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo bit7 bit0 bit7 temp hi: high warning status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit6 temp lo: low warning status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit5 v cc hi: high warning status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit4 v cc lo: low warning status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it will clear itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit3 mon1 hi: high warning status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit2 mon1 lo: low warning status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit1 mon2 hi: high warning status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit0 mon2 lo: low warning status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 39 lower memory, register 75h: warn 2 power-on value 00h read access all write access n/a memory type: volatile 75h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit7 bit0 bit7 mon3 hi: high warning status for mon3 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit6 mon3 lo: low warning status for mon3 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit5 mon4 hi: high warning status for mon4 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit4 mon4 lo: low warning status for mon4 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit3:0 reserved lower memory, register 76h to 77h: reserved power-on value 00h read access all write access n/a memory type: 76, 77h 000000000 bit7 bit0 these registers are reserved. the value when read is 00h.
ds1865 pon triplexer control and monitoring circuit 40 ____________________________________________________________________ lower memory, register 78h: dout power-on value recalled from table 02h, register c0h read access all write access all memory type: volatile 78h reserved reserved reserved reserved d3 out d2 out d1 out d0 out bit7 bit0 at power-on, these bits are defined by the value stored in the dpu byte (table 02h, register c0h). these bits define the value of the logic states of their corresponding output pins. lower memory, register 79h: din power-on value see description read access all write access n/a memory type: volatile 79h reserved reserved inv losi mux losi d3 in d2 in d1 in d0 in bit7 bit0 bit7:6 reserved bit5 inv losi: allows for inversion of losi pin to d0 pin. mux losi bit must be set to 1 or this bit does not affect the output. this bit is controlled (or set) by the dpu byte (table 02h, register c0h). 1 = los buffered out 0 is inverted. bit4 mux losi: determines control of d0 pin. this bit is controlled (or set) by the dpu byte (table 02h, register c0h). 0 = logic value of d0 is controlled by dout byte. 1 = logic value of d0 is controlled by losi pin and inv losi bit. bit3 d3 in: reflects the logic value of d3 pin. bit2 d2 in: reflects the logic value of d2 pin. bit1 d1 in: reflects the logic value of d1 pin. bit0 d0 in: reflects the logic value of d0 pin. lower memory, register 7ah: reserved power-on value 00h read access all write access n/a memory type: 7ah 000000000 bit7 bit0 this register is reserved. the value when read is 00h.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 41 lower memory, register 7bh to 7eh: password entry (pwe) power-on value ffff ffffh read access n/a write access all memory type: volatile 7bh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 7ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 7eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 password entry. there are two passwords for the ds1865. each password is 4 bytes long. the lower level password (pw1) will have access to all unprotected areas plus those made available with pw1. the higher level password (pw2) will have all the access of pw1 plus those made available with pw2. the values of the passwords reside in eeprom inside of pw2 memory. at power-up, all pwe bits are set to 1. all reads at this location are 0. lower memory, register 7fh: table select (tbl sel) power-on value 00h read access all write access all memory type volatile 7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the upper memory tables (table 01h?6h) of the ds1865 are accessible by writing the desired table value in this register.
ds1865 pon triplexer control and monitoring circuit 42 ____________________________________________________________________ table 01h, register 80h to f7h: pw1 eeprom power-on value 00h read access pw1 write access pw1 memory type nonvolatile (ee) 80h-f7h ee ee ee ee ee ee ee ee bit7 bit0 eeprom for pw1 level access. table 01h register descriptions table 01h, register f8h: alarm 3 power-on value 00h read access all write access pw1 memory type: volatile f8h temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo bit7 bit0 layout is identical to alarm 3 in lower memory, register 70h with two exceptions. 1. v cc low alarm is not set at power-on. 2. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register f9h: alarm 2 power-on value 00h read access all write access pw1 memory type: volatile f9h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit7 bit0 layout is identical to alarm 2 in lower memory, register 71h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 43 table 01h, register fah: alarm 1 power-on value 00h read access all write access pw1 memory type: volatile fah reserved reserved reserved bias hi reserved reserved txp hi txp lo bit7 bit0 layout is identical to alarm 1 in lower memory, register 72h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register fbh: alarm 0 power-on value 00h read access all write access pw1 memory type: volatile fbh reserved reserved reserved reserved bias max reserved reserved reserved bit7 bit0 layout is identical to alarm 0 in lower memory, register 73h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register fch: warn 3 power-on value 00h read access all write access pw1 memory type: volatile fch temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo bit7 bit0 layout is identical to warn 3 in lower memory, register 74h with two exceptions. 1. v cc low warning is not set at power-on. 2. these bits are latched. they are cleared by power-down or a write with pw1 access.
ds1865 pon triplexer control and monitoring circuit 44 ____________________________________________________________________ table 01h, register fdh: warn 2 power-on value 00h read access all write access pw1 memory type: volatile fdh mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserved reserved bit7 bit0 layout is identical to warn 2 in lower memory, register 75h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register feh to ffh: reserved power-on value 00h read access all write access pw1 memory type: volatile these registers are reserved.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 45 table 02h, register 80h: mode power-on value 1fh read access pw2 write access pw2 memory type: volatile 80h seeb reserved reserved m4dac-en aen mod-en apc-en bias-en bit7 bit0 bit7 seeb: 0 = (default) enables eeprom writes to see bytes. 1 = disables eeprom writes to see bytes during configuration, so that the configuration of the part is not delayed by the ee cycle time. once the values are known, write this bit to a 0 and write the see locations again for data to be written to the eeprom. bit6:5 reserved bit4 m4dac-en: 0 = m4dac is writeable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for m4dac. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for m4dac. bit3 aen: 0 = the temperature-calculated index value (t index) is writeable by the user and the updates of calculated indexes are disabled. this allows users to interactively test their modules by controlling the indexing for the lookup tables. the recalled values from the luts will appear in the dac registers after the next completion of a temperature conversion (just like it would happen in auto mode). both dacs will update at the same time (just like in auto mode). 1 = (default) enables auto control of the lut. bit2 mod-en: 0 = mod dac is writeable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for modulation. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for modulation. bit1 apc-en: 0 = apc dac is writeable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the dac value for apc reference. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for apc reference. bit0 bias-en: 0 = bias dac is controlled by the user and the apc is open loop. the bias dac value is written to the man ibias register. all values that are written to man ibias and are greater than the max ibias register setting are not updated and will set the bias max alarm bit. the bias dac register will continue to reflect the value of the bias dac. this allows users to interactively test their modules by writing the dac value for i bias . the output is updated with the new value at the end of the write cycle to the man ibias register. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control for the apc feedback. table 02h register descriptions
ds1865 pon triplexer control and monitoring circuit 46 ____________________________________________________________________ table 02h, register 81h: tindex power-on value 00h read access pw2 write access pw2 and (aen = 0) memory type volatile 81h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 holds the calculated index based on the temperature measurement. this index is used for the address during lookup of tables 04h and 05h. temperature measurements below -40? or above 102? are clamped to 00h and c7h, respectively. the calculation of tindex is as follows: table 02h, register 82h: mod dac power-on value 00h read access pw2 write access pw2 and (mod-en = 0) memory type volatile 82h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the digital value used for mod and recalled from table 04h at the adjusted memory address is found in tindex. (r.o.) this register is updated at the end of every temperature conversion. for the two temperature-indexed luts, the index used during the lookup function for each table is as follows: tab l e 04h m od 1 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex 0 tab l e 05h ap c 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex temp c c h = + + 40 2 80 table 02h, register 83h: apc dac power-on value 00h read access pw2 write access pw2 and (apc-en = 0) memory type volatile 83h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the digital value used for apc reference and recalled from table 05h at the adjusted memory address found in tindex. (r.o.) this register is updated at the end of the temperature conversion.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 47 table 02h, register 84h: vindex factory default 00h read access pw2 write access pw2 and (aen = 0) memory type volatile 84h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 holds the calculated index based on the mon4 voltage measurement. this index is used for the address during lookup of table 06h. m4dac lut (table 06h) is 32 bytes from address 80h to 9fh. the calculation of vindex is as follows: table 02h, register 85h: m4dac factory default 00 00h read access pw2 write access pw2 and (m4dac-en = 0) memory type: volatile 85h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the digital value used for m4dac and recalled from table 06h at the adjusted memory address is found in vindex. (r.o.) this register is updated at the end of the mon4 conversion. table 02h, register 86h: device id factory default 65h read access pw2 write access n/a memory type rom 86h 01100101 bit7 bit0 hardwired connections to show device id. when configured as a single lut, all 32 bytes are used for lookup. w hen confi g ur ed as a d oub l e lu t, the fi r st 16 b ytes ( 80h- 8fh) for m the l ow er lu t and the l ast 16 b ytes ( 90h- 9fh) for m the up p er lu t. for the three different modes, the index used during the lookup function of table 06h is as follows: single 1 0 0 vindex 4 vindex 3 vindex 2 vindex 1 vindex 0 double / lower 1 0 0 0 vindex 4 vindex 3 vindex 2 vindex 1 double / upper 1 0 0 1 vindex 4 vindex 3 vindex 2 vindex 1 vindex mon h h =+ 4 800 80
ds1865 pon triplexer control and monitoring circuit 48 ____________________________________________________________________ table 02h, register 87h: device ver factory default device version read access pw2 write access n/a memory type rom 87h device version bit7 bit0 hardwired connections to show device version. table 02h, register 88h: update rate factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) defines the update rate for comparison of apc control. 88h 0 0 0 0 sr 3 sr 2 sr 1 sr 0 bit7 bit0 bit7:4 0: bit3:0 sr(3:0): 4-bit sample rate for comparison of apc control. bit sr 3 ?r 0 minimum time from ben to first sample (t first ) ?0ns repeated sample period following first sample (t rep ) 0000b 350ns 800ns 0001b 550ns 1200ns 0010b 750ns 1600ns 0011b 950ns 2000ns 0100b 1350ns 2800ns 0101b 1550ns 3200ns 0110b 1750ns 3600ns 0111b 2150ns 4400ns 1000b 2950ns 6000ns *1001b 3150ns 6400ns * all codes greater than 1001b (1010b?111b) use the maximum sample time of code 1001b.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 49 table 02h, register 89h: config factory default 00h read access pw2 write access pw2 memory type: nonvolatile (see) 89h fetg dir tx-f en reserved asel reserved reserved reserved reserved bit7 bit0 configure the memory location and the polarity of the digital outputs. bit7 fetg dir: chooses the direction or polarity of the fetg output for normal operation. 0 = (default) under normal operation, fetg is pulled low. intended for use with nmos. 1 = under normal operation, fetg is pulled high. intended for use with pmos. bit6 tx-f en: the tx-f output pin always reflects the wired-or of all txf enabled alarm states. this bit will enable the latching of the alarm state for the txf output pin. 0 = (default) not latched. 1 = the alarm bits are latched until cleared by a tx-d transition or power-down. if v cc _lo_alarm is enabled for either fetg or tx-f then latching is disabled until the after the first v cc measurement is made above the v cc _lo set point to allow for proper operation during slow power-on cycles. bit5 reserved bit4 asel: address select. 0 = (default) device address of a2h. 1 = i 2 c slave address is determined by the value programmed in the device address byte (table 02h, register 8ch). bit3:0 reserved table 02h, register 8ah: startup step factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8ah 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 bit7 bit0 this value will define the maximum allowed step for the upper 8 bits of i bias output during startup. programming this value to 00h cause the device to take single lsb (2 0 ) steps towards convergence. see the bias and mod output during power-up section for details.
ds1865 pon triplexer control and monitoring circuit 50 ____________________________________________________________________ table 02h, register 8bh: mod ranging factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8bh reserved reserved reserved reserved reserved mod 2 mod 1 mod 0 bit7 bit0 the lower nibble of this byte controls the full-scale range of the modulation dac. bit7:3 reserved (default = 0) bit2:0 mod 2 , mod 1 , mod 0 : mod fs ranging. 3-bit value to select the fs output voltage for vmod. default is 000b and creates a fs of 1.25v. mod 2 ?mod 0 % of 1.25v fs voltage ( v ) 000b 100.00 1.250 001b 80.05 1.001 010b 66.75 0.833 011b 50.13 0.627 100b 40.16 0.502 101b 33.50 0.419 110b 28.75 0.359 111b 25.18 0.315 table 02h, register 8ch: device address factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8ch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this value becomes the i 2 c slave address for the main memory when the asel bit (table 02h, register 89h) is set.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 51 table 02h, register 8dh: comp ranging factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8dh reserved bias 2 bias 1 bias 0 reserved apc 2 apc 1 apc 0 bit7 bit0 the upper nibble of this byte controls the full-scale range of the quick-trip monitoring for bias. the lower nibble of this byt e controls the full-scale range for the quick-trip monitoring of the apc reference as well as the closed loop monitoring of apc. bit7 reserved (default = 0) bit6.4 bias 2 , bias 1 , bias 0 : bias fs ranging: 3-bit value to select the fs comparison voltage for bias found on mon1. default is 000b and creates an fs of 1.25v. bit3 reserved (default = 0) bit2:0 apc 2 , apc 1 , apc 0 : apc fs ranging: 3-bit value to select the fs comparison voltage for bmd with the apc. default is 000b and creates an fs of 2.5v. bias 2 ?bias 0 % of 1.25v fs voltage ( v ) 000b 100.00 1.250 001b 80.10 1.001 010b 66.83 0.835 011b 50.25 0.628 100b 40.30 0.504 101b 33.66 0.421 110b 28.92 0.362 111b 25.39 0.317 apc 2 ?apc 0 % of 2.50v f s vo l t a g e ( v ) 000b 100.00 1.250 001b 80.10 1.001 010b 66.83 0.835 011b 50.25 0.628 100b 40.30 0.504 101b 33.66 0.421 110b 28.92 0.362 111b 25.39 0.317
ds1865 pon triplexer control and monitoring circuit 52 ____________________________________________________________________ table 02h, register 8eh: right shift 1 (rshift 1 ) factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8eh reserved mon1 2 mon1 1 mon1 0 reserved mon2 2 mon2 1 mon2 0 bit7 bit0 allows for right-shifting the final answer of mon1 and mon2 voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. see the right shifting adc results section for details. table 02h, register 8fh: right shift 0 (rshift 0 ) factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8fh reserved mon3 2 mon3 1 mon3 0 reserved mon4 2 mon4 1 mon4 0 bit7 bit0 allows for right-shifting the final answer of mon3 and mon4 voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. see the right shifting adc results section for details. table 02h, register 90h to 91h: reserved factory default: 0000h read access pw2 write access pw2 memory type: nonvolatile (see) these registers are reserved.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 53 table 02h, register 92h to 93h: v cc scale table 02h, register 94h to 95h: mon1 scale table 02h, register 96h to 97h: mon2 scale table 02h, register 98h to 99h: mon3 scale table 02h, register 9ah to 9bh: mon4 scale factory calibrated read access pw2 write access pw2 memory type: nonvolatile (see) 92, 94, 96, 98, 9ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93, 95, 97, 99, 9bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 controls the scaling or gain of the fs voltage measurements. the factory-calibrated value produces an fs voltage of 6.5536v for v cc and 2.5v for mon1, mon2, mon3, and mon4. table 02h, register 9ch to a1h: reserved factory default: 0000h read access pw2 write access pw2 memory type: nonvolatile (see) these registers are reserved. table 02h, register a2h to a3h: v cc offset table 02h, register a4h to a5h: mon1 offset table 02h, register a6h to a7h: mon2 offset table 02h, register a8h to a9h: mon3 offset table 02h, register aah to abh: mon4 offset factory default: 0000h read access pw2 write access pw2 memory type: nonvolatile (see) a2, a4, a6, a8, aah ss2 15 2 14 2 13 2 12 2 11 2 10 a3, a5, a7, a9, abh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit7 bit0 allows for offset control of these voltage measurements if desired.
ds1865 pon triplexer control and monitoring circuit 54 ____________________________________________________________________ table 02h, register ach to adh: reserved factory default: 0000 0000h read access pw2 write access pw2 memory type: nonvolatile (see) these registers are reserved. table 02h, register aeh to afh: internal temp offset factory calibrated read access pw2 write access pw2 memory type nonvolatile (see) aeh s2 8 2 7 2 6 2 5 2 4 2 3 2 2 afh 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 bit7 bit0 allows for offset control of the temperature measurement if desired. the final result must be xored with bb40h before writing t o this register. factory calibration contains the desired value for a reading in degrees celsius. table 02h, register b0h to b3h: pw1 factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b0h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b1h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b2h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the pwe value is compared against the value written to this location to enable pw1 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones grants pw1 access on power-up without writing the password entry. all reads of this register are 00h.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 55 table 02h, register b4h to b7h: pw2 factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b4h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b5h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b6h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the pwe value is compared against the value written to this location to enable pw2 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones grants pw2 access on power-up without writing the password entry. all reads of this register are 00h.
ds1865 pon triplexer control and monitoring circuit 56 ____________________________________________________________________ table 02h, register b8h: fetg enable 1 (fetg en 1 ) factory default 00h read access pw2 write access pw2 memory type: nonvolatile (see) b8h temp en v cc en mon1 en mon2 en mon3 en mon4 en reserved reserved bit7 bit0 configures the maskable interrupt for the fetg pin. bit7 temp en: enables/disables active interrupts on the fetg pin due to temperature measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit6 v cc en: enables/disables active interrupts on the fetg pin due to v cc measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit5 mon1 en: enables/disables active interrupts on the fetg pin due to mon1 measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit4 mon2 en: enables/disables active interrupts on the fetg pin due to mon2 measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit3 mon3 en: enables/disables active interrupts on the fetg pin due to mon3 measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit2 mon4 en: enables/disables active interrupts on the fetg pin due to mon4 measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit1:0 reserved (default = 0)
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 57 table 02h, register b9h: fetg enable 0 (fetg en 0 ) factory default 00h read access pw2 write access pw2 memory type: nonvolatile (see) b9h htxp en ltxp en bias-hi en bias max en reserved reserved reserved reserved bit7 bit0 configures the maskable interrupt for the fetg pin. bit7 htxp en: enables/disables active interrupts on the fetg pin due to txp fast comparisons above the threshold limit. 0 = disable (default). 1 = enable. bit6 ltxp en: enables/disables active interrupts on the fetg pin due to txp fast comparisons below the threshold limit. 0 = disable (default). 1 = enable. bit5 bias hi en: enables/disables active interrupts on the fetg pin due to bias fast comparisons above the threshold limit. 0 = (default) disable. 1 = enable. bit4 bias max en: enables/disables active interrupts on the fetg pin due to bias fast comparisons below the threshold limit. 0 = (default) disable. 1 = enable. bit3:0 reserved (default = 0)
ds1865 pon triplexer control and monitoring circuit 58 ____________________________________________________________________ table 02h, register bah: tx-f enable 1 (tx-f en 1 ) factory default 00h read access pw2 write access pw2 memory type: nonvolatile (see) bah temp en v cc en mon1 en mon2 en mon3 en mon4 en reserved reserved bit7 bit0 configures the maskable interrupt for the tx-f pin. bit7 temp en: enables/disables active interrupts on the tx-f pin due to temperature measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit6 v cc en: enables/disables active interrupts on the tx-f pin due to v cc measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit5 mon1 en: enables/disables active interrupts on the tx-f pin due to mon1measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit4 mon2 en: enables/disables active interrupts on the tx-f pin due to mon2 measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit3 mon3 en: enables/disables active interrupts on the tx-f pin due to mon3 measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit2 mon4 en: enables/disables active interrupts on the tx-f pin due to mon4 measurements outside the threshold limits. 0 = disable (default). 1 = enable. bit2:0 reserved (default = 0)
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 59 table 02h, register bbh: tx-f enable 0 (tx-f en 0 ) factory default 00h read access pw2 write access pw2 memory type: nonvolatile (see) bbh htxp en ltxp en bias-hi en bias max en reserved reserved reserved fetg en bit7 bit0 configures the maskable interrupt for the tx-f pin. bit7 htxp en: enables/disables active interrupts on the tx-f pin due to txp fast comparisons above the threshold limit. 0 = disable (default). 1 = enable. bit6 ltxp en: enables/disables active interrupts on the tx-f pin due to txp fast comparisons below the threshold limit. 0 = disable (default). 1 = enable. bit5 bias-hi en: enables/disables active interrupts on the tx-f pin due to bias fast comparisons above the threshold limit. 0 = disable (default). 1 = enable. bit4 bias max en: enables/disables active interrupts on the tx-f pin due to bias fast comparisons above the threshold limit. 0 = disable (default). 1 = enable. bit3:1 reserved (default = 0) bit0 fetg en: 0 = normal fetg operation (default). 1 = enables fetg to act as an input to tx-f output.
ds1865 pon triplexer control and monitoring circuit 60 ____________________________________________________________________ table 02h, register bch: htxp factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) bch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 fast-comparison dac threshold adjust for high transmit power. this value is added to the apc_dac value recalled from table 04h. if the sum is greater than 0xff, 0xff is used. comparisons greater than apc_dac plus this value, found on the bmd pin, will create a txp-hi alarm. table 02h, register bdh: ltxp factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) bdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 fast-comparison dac threshold adjust for low transmit power. this value is subtracted from the apc_dac value recalled from table 04h. if the difference is less than 0x00, 0x00 is used. comparisons less than apc_dac minus this value, found on the bmd pin, create a txp-lo alarm. table 02h, register beh: hbias factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) beh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 fast- com p ar i son d ac setti ng for hi g h bias . c om p ar i sons g r eater than thi s val ue, found on the m on 1 p i n, cr eate a bias h i al ar m . table 02h, register bfh: max ibias factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) bfh 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 bit7 bit0 thi s val ue d efi nes the m axi m um d ac val ue al l ow ed for the up p er 8 b i ts of i b ia s outp ut d ur i ng al l op er ati ons. d ur i ng the i nti al step and b i nar y sear ch, thi s val ue w i l l not cause an al ar m b ut w i l l sti l l cl am p the i b ia s d ac outp ut. after the star tup seq ence ( or nor m al ap c op er ati ons) , i f the ap c l oop tr i es to cr eate an i b ia s val ue g r eater than thi s setti ng , i t i s cl am p ed and cr eates a bias m ax al ar m . s etti ng s 00h thr oug h fe h ar e i ntend ed for nor m al ap c m od e of op er ati on. s etti ng ffh i s r eser ved for m anual ibias m od e.
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 61 table 02h, register c0h: dpu factory default 00h read access pw2 write access pw2 memory type: nonvolatile (see) c0h reserved reserved inv losi mux losi d3 cntl d2 cntl d1 cntl d0 cntl bit7 bit0 controls the power-on values for d3, d2, d1, and d0 output pins and mux and invertion of the losi pin. bit7:6 reserved bit5 inv losi: inverts the buffered input pin losi to output pin d0 if mux losi is set. if mux losi is not set then this bit? value is a don? care. 0 = (default) noninverted losi to d0 pin. 1 = inverted losi to d0 pin. bit4 mux losi: chooses the control for d0 output pin. 0 = (default) do is controlled by bit d0 out found in lower memory, register 78h. 1 = losi is buffered to d0 pin. bit3 d3 cntl: at power-on, this value is loaded into bit d3 out of lower memory, register 78h to control the output pin d3. bit2 d2 cntl: at power-on, this value is loaded into bit d2 out of lower memory, register 78h to control the output pin d2. bit1 d1 cntl: at power-on, this value is loaded into bit d1 out of lower memory, register 78h to control the output pin d1. bit0 d0 cntl: at power-on, this value is loaded into bit d0 out of lower memory, register 78h to control the output pin d0. table 02h, register c1h to c3h: reserved factory default: 0000 0000h read access pw2 write access pw2 memory type: nonvolatile (see) these registers are reserved. table 02h, register c4h: dac1 factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) c4h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 register to control dac1.
ds1865 pon triplexer control and monitoring circuit 62 ____________________________________________________________________ table 02h, register c5h to c6h: reserved factory default: 0000 0000h read access pw2 write access pw2 memory type: nonvolatile (see) these registers are reserved. table 02h, register c7h: m4 lut cntl factory default 00h read access pw2 write access pw2 memory type: nonvolatile (see) c7h reserved reserved reserved reserved reserved reserved dbl_sb up_lowb bit7 bit0 controls the size and location of lut functions for the mon4 measurement. bit7:2 reserved: default = 000000b. bit1 dbl_sb: chooses the size of lut for table 06h. 0 = (default) single lut of 32 bytes. 1 = double lut of 16 bytes. bit0 up_lowb: determines which 16-byte lut is used if dbl_sb = 1. if dbl_sb = 0, the value of this bit is a don? care. 0 = (default) chooses the lower 16 bytes of table 06h (registers 80h-8fh). 1 = chooses the upper 16 bytes of table 06h (registers 90h-9fh). table 02h, register c8h to f7h: no memory table 02h, register f8h to f9h: man ibias factory default: 00h read access pw2 write access pw2 and (bias-en = 0) memory type: volatile f8h reserved reserved 2 12 2 11 2 10 2 9 2 8 2 7 f9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 w hen bias - e n ( tab l e 02h, reg i ster 80h) i s w r i tten to 0, w r i tes to these b ytes w i l l contr ol the i b ia s d ac . s ee m an _c n tl ( tab l e 02h, reg i ster fah) for d etai l s.
pon triplexer control and monitoring circuit ____________________________________________________________________ 63 table 02h, register fah: man_cntl factory default: 00h read access pw2 write access pw2 and (bias-en = 1) memory type: volatile fah reserved reserved reserved reserved reserved reserved reserved man_clk bit7 bit0 when bias-en (table 02h, register 80h) is written to zero, bit zero of this byte will control the updates of the man ibias valu e to the bias output. the values of man ibias should be written with a separate write command. setting bit zero to a 1 will clock th e man ibias value to the output dac for control of i bias . 1. write the man ibias value with a write command. 2. set the man_clk bit to a 1 with a separate write command. 3. clear the man_clk bit to a 0 with a separate write command. table 02h, register fbh to fch: bias dac factory default: 00 00h read access pw2 write access n/a memory type: nonvolatile (see) fbh 002 12 2 11 2 10 2 9 2 8 2 7 fch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the digital value indicating the dac value used for i bias output. table 02h, register fdh to ffh: reserved factory default: read access pw2 write access n/a memory type: fdh 00000000 feh 0000000x ffh xxxxxxxx bit7 bit0 these registers are reserved.
ds1865 pon triplexer control and monitoring circuit 64 ____________________________________________________________________ table 03h, register 80h to ffh: pw2 eeprom factory default 00h read access pw2 write access pw2 memory type: nonvolatile (ee) 80h-ffh ee ee ee ee ee ee ee ee bit7 bit0 pw2 protected eeprom. table 04h, register 80h to c7h: mod lut factory default 00h read access pw2 write access pw2 memory type: nonvolatile (ee) 80h-c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the digital value for the modulation dac output. the modulation lut is a set of registers assigned to hold the temperature profile for the modulation dac. the values in this ta ble combined with the mod bits in the mod ranging register (table 02h, register 8bh) determine the set point for the modulation voltage. the temperature measurement is used to index the lut (t index, table 02h, register 81h) in 2? increments from -40? to +102?, starting at 80h in table 04h. register 80h defines the -40? to -38? mod output, register 81h defines -38? to -36 c mod output, and so on. values recalled from this eeprom memory table are written into the mod_dac (table 02h, register 82h) location that holds the value until the next temperature conversion. the part can be placed into a manual mode (mod-en bit, tab le 02h, register 80h), where mod_dac is directly controlled for calibration. if the temperature compensation functionality is not required, then program the entire table 04h to the desired modulation setting. table 03h register descriptions table 04h register descriptions
ds1865 pon triplexer control and monitoring circuit ____________________________________________________________________ 65 table 05h, register 80h to a3h: apc tracking error lut (apc ref) factory default 00h read access pw2 write access pw2 memory type: nonvolatile (ee) 80h-a3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the tracking error lut is set of registers assigned to hold the temperature profile for the apc reference dac. the values in th is table combined with the apc bits in the comp ranging register (table 02h, register 8dh) determine the set point for the apc loo p. the temperature measurement is used to index the lut (t index, table 02h, register 81h) in 4? increments from -40? to +100?, starting at register 80h in table 05h. register 80h defines the -40? to -36? apc reference value, register 81h define s -36? to -32? apc reference value, and so on. values recalled from this eeprom memory table are written into the apc dac (table 02h, register 83h) location that holds the value until the next temperature conversion. the part can be placed into a ma nual mode (apc-en bit, table 02h, register 80h), where apc dac can be directly controlled for calibration. if tracking error temperature compensation is not required by the application, program the entire lut to the desired apc set point. table 05h register descriptions table 05h, register a4h to a7h: reserved factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) these registers are reserved.
ds1865 pon triplexer control and monitoring circuit 66 ____________________________________________________________________ table 06h, register 80h to 9fh: m4dac lut factory default 00h read access pw2 write access pw2 memory type: nonvolatile (ee) 80h-9fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the m4dac lut is set of registers assigned to hold the voltage profile for the m4dac. the values in this table determine the se t point for the m4dac. the mon4 voltage measurement is used to index the lut (vindex, table 02h, register 84h), starting at register 80h in table 06h. values recalled from this eeprom memory table are written into the m4dac (table 02h, register 85h) location that holds the value until the next mon4 voltage conversion. the part can be placed into a manual mode (m4dac-en bit, table 02h, register 80h), where m4dac is directly controlled for calibration. if voltage compensation is not required by the application, program the entire lut to the desired m4dac set point. table 06h register descriptions auxiliary memory a0h, register 00h to 7fh: eeprom factory default 00h read access pw2 write access pw2 memory type: nonvolatile (ee) 00h-7fh ee ee ee ee ee ee ee ee bit7 bit0 eeprom auxiliary memory a0h register descriptions package type package code document no. 28 tqfn-ep t2855+8 21-0140 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to th e package regardless of rohs status.
ds1865 pon triplexer control and monitoring circuit maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 67 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. revision history revision number revision date description pages changed 0 3/07 initial release 1 11/09 changed the high voltage parameter from +5.5v to +3.9v 1C6

▲Up To Search▲

Price & Availability of DS1865T

	To Download DS1865T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .